1. Field of the Invention
The present invention generally relates to methods of manufacture of trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs) as used in dynamic random access memory (DRAM) technologies and, more particularly, to methods for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width.
2. Description of the Prior Art
Corner conduction in trench isolated n-channel MOSFETs, as reported by A. Bryant, W. Haensch, S. Geissler, J. Mandelman, D. Poindexter, and M. Steger in "The Current-Carrying Corner Inherent to Trench Isolation", IEEE Electron Device Letters, vol. 14, no. 8, pp. 412-414 (1993), and B. Davari, C. Koburger, T. Furukawa, Y. Taur, W. Noble, J. Warnock, and J. Mauer in "A Variable-Size Shallow Trench Isolation (STI) Technology with Diffused Sidewall Doping for Submicron CMOS", 1988 IEDM Technical Digest, pp. 92-95 (1988), could be a significant contributor to standby current in low standby power ultra large scale integration (ULSI) applications. A manifestation of corner conduction is inverse narrow channel effect when the standard current definition of threshold voltage, V.sub.t, ##EQU1##
is applied, where W.sub.des and L.sub.des are the design width and design length of the device, respectively. Using V.sub.t defined by the above equation, inverse narrow channel effect is characterized by a decrease in the magnitude of V.sub.t as the width of the device decreases.
However, corner conduction in buried-channel p-MOSFETs has not, heretofore, been recognized as a concern. In buried-channel p-MOSFETs, the polarity of the work function difference between the N+ poly gate and the buried p-layer depletes the buried layer of carriers at low gate voltages. Due to the geometrically enhanced field at the silicon corner, it is expected that, when doping is uniform across the device width, the magnitude of V.sub.t at the corners of these devices is greater than at mid-channel. This leads to a normal channel effect, wherein the magnitude of V.sub.t increases with decreasing width of the device.
An anomalous (or inverse) narrow channel behavior has been observed in trench-bounded buried-channel p-MOSFETs (as used in contemporary DRAM technologies). Specifically, it has been observed that the magnitude of the threshold voltage, V.sub.t, drops by approximately 100 mV when going from a device width of 20 .mu.m down to 2 .mu.m. The magnitude of V.sub.t drops more rapidly with further width reduction to approximately 0.4,.mu.m. For devices narrower than 0.4.mu.m, the expected normal narrow channel effect is observed, that is, the magnitude of V.sub.t increases with decreasing width of the device.
If the buried-channel boron dose is decreased to assure that the off-current is less than or equal to the objective over the entire range of design widths, the performance of the widest devices is compromised as a result of the higher than desired V.sub.t. Consequently, to assure that the narrowest devices meet the off-current objective, the magnitude of the V.sub.t of the widest devices must be set higher than required by the off-current objective. This results in a performance penalty for the wider devices of typically a 100 mV loss of overdrive.